ddu222f doc #97011 data delay devices, inc. 1 1/27/97 3 mt. prospect ave. clifton, nj 07013 5-tap, ttl-interfaced fixed delay line (series ddu222f) features packages five equally spaced outputs very narrow device (sip package) stackable for pc board economy input & outputs fully ttl interfaced & buffered 10 t 2 l fan-out capability functional description the ddu222f-series device is a 5-tap digitally buffered delay line. the signal input (in) is reproduced at the outputs (t1-t5), shifted in time by an amount given by the device dash number. for dash numbers less than 25, the total delay of the line is measured from t1 to t5, with the nominal value given by the dash number. the nominal tap-to-tap delay increment is given by 1/4 of this number. the inherent delay from in to t1 is nominally 3.5ns. for dash numbers greater than or equal to 25, the total delay of the line is measured from in to t5, with the nominal value given by the dash number. the nominal tap-to-tap delay increment is given by 1/5 of this number. series specifications minimum input pulse width: 40% of total delay output rise time: 2ns typical supply voltage: 5vdc 5% supply current: i ccl = 32ma typical i cch = 7ma typical operating temperature: 0 to 70 c temp. coefficient of total delay: 100 ppm/ c 25% 25% 25% 25% vcc gnd in t1 t2 t3 t4 t5 functional diagram for dash numbers < 25 3.5ns 20% 20% 20% 20% 20% vcc gnd in t1 t2 t3 t4 t5 functional diagram for dash numbers >= 25 1997 data delay devices data delay devices, inc. 3 2 3 4 5 6 7 8 1 vcc in t1 t2 t3 t4 t5 gnd ddu222f-xx commercial ddu222f-xxm military pin descriptions in signal input t1-t5 tap outputs vcc +5 volts gnd ground dash number specifications part number total delay ( ns) delay per tap ( ns) ddu222f-4 4 1.0 * 1.0 0.5 ddu222f-6 6 1.0 * 1.5 0.5 ddu222f-8 8 2.0 * 2.0 1.0 DDU222F-10 10 2.0 * 2.5 1.0 ddu222f-12 12 2.0 * 3.0 1.0 ddu222f-16 16 2.0 * 4.0 1.5 ddu222f-25 25 3.0 5.0 2.0 ddu222f-30 30 3.0 6.0 2.0 ddu222f-35 35 3.0 7.0 2.0 ddu222f-40 40 3.0 8.0 2.0 ddu222f-45 45 3.0 9.0 3.0 ddu222f-50 50 3.0 10.0 3.0 ddu222f-60 60 3.0 12.0 3.0 ddu222f-75 75 4.0 15.0 3.0 DDU222F-100 100 5.0 20.0 3.0 ddu222f-125 125 6.5 25.0 3.0 ddu222f-150 150 7.5 30.0 3.0 ddu222f-175 175 8.0 35.0 4.0 ddu222f-200 200 10.0 40.0 4.0 ddu222f-250 250 12.5 50.0 5.0 * total delay is referenced to first tap output input to first tap = 3.5ns 1ns note: any dash number between 4 and 250 not shown is also available.
ddu222f doc #97011 data delay devices, inc. 2 1/27/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes high frequency response the ddu222f tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. however, for a given input condition, the deviation will be repeatable from pulse to pulse. contact technical support at data delay devices if your application requires device testing at a specific input condition. power supply bypassing the ddu222f relies on a stable power supply to produce repeatable delays within the stated tolerances. a 0.1uf capacitor from vcc to gnd, located as close as possible to the vcc pin, is recommended. a wide vcc trace and a clean ground plane should be used. device specifications table 1: absolute maximum ratings parameter symbol min max units notes dc supply voltage v cc -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 2: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min typ max units notes high level output voltage v oh 2.5 3.4 v v cc = min, i oh = max v ih = min, v il = max low level output voltage v ol 0.35 0.5 v v cc = min, i ol = max v ih = min, v il = max high level output current i oh -1.0 ma low level output current i ol 20.0 ma high level input voltage v ih 2.0 v low level input voltage v il 0.8 v input clamp voltage v ik -1.2 v v cc = min, i i = i ik input current at maximum input voltage i ihh 0.1 ma v cc = max, v i = 7.0v high level input current i ih 20 m a v cc = max, v i = 2.7v low level input current i il -0.6 ma v cc = max, v i = 0.5v short-circuit output current i os -60 -150 ma v cc = max output high fan-out 25 unit output low fan-out 12.5 load
ddu222f doc #97011 data delay devices, inc. 3 1/27/97 3 mt. prospect ave. clifton, nj 07013 package dimensions .300 max. .100 min. .900 max. 1 2 3 4 5 6 7 .200 max. .020 typ. .020 typ. .700 typ. .100 typ. .010 typ. 8 ddu222f-xx (commercial) .375 max. .150 .030 .005 min. .018 typ. .700 typ. .100 typ. .010 typ. .900 max. 1 2 3 4 5 6 7 .200 max. 8 ddu222f-xxm (military)
ddu222f doc #97011 data delay devices, inc. 4 1/27/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 1 fast-ttl gate supply voltage ( vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 w max. rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.5 x total delay period: per in = 10 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. t1 out trig in ref trig test setup device under test (dut) time interval counter pulse generator computer system printer in t2 t3 t4 t5 timing diagram for testing t rise t fall per in pw in t rise t fall 0.6v 0.6v 1.5v 1.5v 2.4v 2.4v 1.5v 1.5v v ih v il v oh v ol input signal output signal
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